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this is information on a product in full production. september 2012 doc id 018878 rev 2 1/12 12 DVIULC6-4SC6Y automotive ultralow capacitance esd protection datasheet ? production data features 4-line esd protection (iec 61000-4-2) protects v bus when applicable ultralow capacitance: 0.6 pf at f = 825 mhz fast response time compared with varistors rohs compliant aec-q101 qualified benefits esd protection of v bus optimized rise and fall times for maximum data integrity consistent d+ / d- signal balance: ? optimum capacitance matching tolerance for ultralow intra pair skew: i/o to ground = 0.015 pf, i/o to i/o = 0.007 pf ? matching high bit rate dvi, hdmi, and idb 1394 bus requirements low pcb space occupation: 9 mm 2 higher reliability offered by monolithic integration complies with these standards iso 10605 (c = 330 pf, r = 330 ?? ? 18 kv (air discharge) ? 18 kv (contact discharge) iso 10605 (c = 150 pf, r = 330 ?? ? 18 kv (air discharge) ? 18 kv (contact discharge) mil std883g-method 3015-7 iso 7637-2 ? pulse 3a: v s = -150 v ? pulse 3b: v s = 100 v applications dvi ports up to 1.65 gb/s hdmi ports up to 1.65 gb/s idb 1394 usb 2.0 ports up to 480 mb/s (high speed), backwards compatible wi th usb1.1 low and full speed ethernet port: 10/100/1000 mb/s sim card protection video line protection description the DVIULC6-4SC6Y is a monolithic, application specific discrete device dedicated to esd protection of high speed interfaces, such as dvi, hdmi, idb 1394 bus, usb2.0, ethernet links and video lines. its ultralow line capacitance secures a high level of signal integrity wit hout compromise in protecting sensitive chips against the most stringently characterized esd strikes. sot23-6l (jedec mo178ab) www.st.com
characteristics DVIULC6-4SC6Y 2/12 doc id 018878 rev 2 1 characteristics figure 1. functional diagram table 1. absolute ratings symbol parameter value unit v pp peak pulse voltage iso 10605 (c = 330 pf, r = 330 ?? air discharge contact discharge iso 10605 (c = 150 pf, r = 330 ?? air discharge contact discharge mil std883g-method 3015-7 18 18 18 18 25 kv t stg storage temperature range -65 to +150 c t j operating junction temperature range -40 to +150 c t l lead solder temperature (10 seconds duration) 260 c table 2. electrical characteristics (t amb = 25 c) symbol parameter test conditions value unit min. typ. max. i rm leakage current v rm = 5 v 0.5 a v br breakdown voltage between v bus and gnd i r = 1 ma 6 v v cl clamping voltage i pp = 1 a, t p = 8/20 s any i/o pin to gnd 12 v i pp = 5 a, t p = 8/20 s any i/o pin to gnd 17 v c i/o-gnd capacitance between i/o and gnd v r = 0 v, f= 1 mhz 0.85 1 pf v r = 0 v, f= 825 mhz 0.6 ? c i/o- gnd capacitance variation between i/o and gnd 0.015 c i/o-i/o capacitance between i/o v r = 0 v, f= 1 mhz 0.42 0.5 pf v r = 0 v, f= 825 mhz 0.3 ? c i/o-i/o capacitance variation between i/o 0.007 1 1 6 2 5 3 4 i/o1 i/o4 gnd v bus i/o2 i/o3
DVIULC6-4SC6Y characteristics doc id 018878 rev 2 3/12 figure 2. line capacitance versus line voltage (typical values) figure 3. line capacitance versus frequency (typical values) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f=825mhz v osc = 500mv rms v bus open t j =25 c 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 data line voltage (v) c i/o - gnd c(pf) 0 v osc =30mv rms t j =25 c v i-o/gnd = 0v f(mhz) 1 10 100 1000 10000 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 c(pf) c i/o - gnd c i/o -c i/o v open bus figure 4. relative variation of leakage current versus junction temperature (typical values) figure 5. frequency response 1.0m 10.0m 100.0m 1.0g - 15.00 - 12.00 - 9.00 - 6.00 - 3.00 0.00 ligne 1 s21(db) f(hz) 1.0m 10.0m 100.0m 1.0g - 15.00 - 12.00 - 9.00 - 6.00 - 3.00 0.00 ligne 1 s21(db) f(hz) figure 6. remaining voltage after the DVIULC6-4SC6Y during positive esd surge (1) figure 7. remaining voltage after the DVIULC6-4SC6Y during negative esd surge (1) 1. measurements were done with dviulc-4sc6 in open circuit
characteristics DVIULC6-4SC6Y 4/12 doc id 018878 rev 2 figure 8. analog crosstalk results 100.0k 1.0m 10.0m 100.0m 1.0g - 120.00 - 90.00 - 60.00 - 30.00 0.00 db f (hz) figure 9. iso 7637-2 pulse 3a response (v s = -150 v) figure 10. iso 7637-2 pulse 3b response (v s = 100 v) -15 -10 -5 0 5 10 15 - 0.1 0.1 0.3 0.5 0.7 0.9 time (s) voltage dviucl6-4sc6y dviucl6-4sc6y voltage (v) -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -0.1 0.1 0.3 0.5 0.7 0.9 time (s) current current (a) - 0.1 0.1 0.3 0.5 0.7 0.9 dviucl6-4sc6y dviucl6-4sc6y voltage (v) - 0.1 0.1 0.3 0.5 0.7 0.9 current (a) -10 0 10 20 30 40 50 time (s) voltage -0.4 -0.2 0 0.2 0.4 0.6 time (s) current
DVIULC6-4SC6Y application examples doc id 018878 rev 2 5/12 2 application examples more information is available in the stmicroe lectronics application note an2689 ?protection of automotive electronics from electrical hazards, guidelines for design and component selection?. figure 11. dvi/hdmi digital single link application figure 12. t1/e1/ethernet protection 1 1 6 2 5 3 4 1 1 6 2 5 3 4 1 1 6 2 5 3 4 1 1 6 2 5 3 4 de de pixel data pixel data clock clock vsync vsync hsync hsync graphics controller tmds transmitter tmds receiver display controller host (pc, graphics cards, set-top box, dvd player) display (lcd monitor, flat panel,display, projector) rx0- tx0- rx0+ tx0+ rx1- rx1+ rx2- rx2+ tx1- tx1+ tx2- tx2+ rc- tc- rc+ tc+ tmds links dvi connector +v cc 100nf data transceiver smp75-8 smp75-8 tx rx 1 1 6 2 5 3 4
technical information DVIULC6-4SC6Y 6/12 doc id 018878 rev 2 3 technical information 3.1 surge protection the DVIULC6-4SC6Y is particularly optimized to perform esd surge protection based on the rail to rail topology. the clamping voltage v cl can be calculated as follows: v cl + = v bus + v f , for positive surges v cl - = - v f , for negative surges with: v f = v t + r d .i p (v f = forward drop voltage) / (v t = forward drop threshold voltage) calculation example we can assume that the value of the dynamic resistance of the clamping diode is typically: r d = 1.4 ? and v t = 1.2 v. for an iec 61000-4-2 surge level 4 (contact discharge: v g = 8 kv, r g = 330 ? ), v bus = +5 v, and, in a first approximation, we assume that: i p = v g / r g = 24 a. we find: v cl + = +39 v v cl - = -34 v note: the calculations do not take into account phenomena due to parasitic inductances. 3.2 surge protection application example if we consider that the connections from the pin v bus to v cc and from gnd to pcb gnd plane are two tracks 10 mm long and 0.5 mm wide, we can assume that the parasitic inductances, l w of these tracks are about 6 nh. so when an iec 61000-4-2 surge occurs, due to the rise time of this spike (tr = 1 ns), the voltage v cl has an extra value equal to l w .di/dt. the di/dt is calculated as: di/dt = i p /t r = 24 a/ns for an iec 61000-4-2 surge level 4 (contact discharge v g = 8 kv, r g = 330 ?? the over voltage due to the parasitic inductances is: l w .di/dt = 6 x 24 = 144 v by taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: v cl + = +39 + 144 = 183 v v cl - = -34 - 144 = -178 v we can reduce as much as possible these phenomena with simple layout optimization. this is the reason why some recommendations have to be followed (see section 3.3: how to ensure good esd protection ).
DVIULC6-4SC6Y technical information doc id 018878 rev 2 7/12 3.3 how to ensure good esd protection while the DVIULC6-4SC6Y provides a high immunity to esd surge, an efficient protection depends on the layout of the board. in the same way, with the rail to rail topology, the track from v bus pin to the power supply +v cc , and from v bus pin to gnd pin must be as short as possible to avoid over voltages due to parasitic phenomena (see figure 13 and figure 14 for layout considerations). figure 13. iesd behavior: parasitic phenomena due to unsuitable layout figure 14. esd behavior: layout optimization and addition of a 100 nf capacitor lw vi/o esd surge gnd i/o +v cc v bus v f lw di dt lw di dt v+ = cl v +v +lw bus f di dt surge >0 di dt surge <0 v- = cl -v -lw f t tr=1ns vv cc f + lw di dt v cl + positive surge 183v -lw di dt t tr=1ns - v f v cl - negative surge -178v ref1=gnd vi/o esd surge i/o ref2=+ v cc c=100nf lw v+ v cl cc f v+ = surge >0 surge <0 vv cl f - - = t v+ cl positive surge t v- cl negative surge
technical information DVIULC6-4SC6Y 8/12 doc id 018878 rev 2 figure 15. pcb layout considerations (v cc connection is application dependent) it?s often harder to connect the power supply near to the DVIULC6-4SC6Y unlike the ground thanks to the ground plane that allows a short connection. to ensure the same efficiency for positive surges when the connections can?t be short enough, we recommend to put close to the DVIULC6-4SC6Y, between v bus and ground, a capacitance of 100 nf to prevent from these kinds of overfatigue disturbances (see figure 14 and figure 15 ). the addition of this ca pacitance will allow a better protection by providing a constant voltage during a surge. figure 16 , figure 6 , and figure 7 show the improvement of the esd protection according to the recommendations described in section 3.3 . figure 16. esd behavior: measurement conditions (with coupling capacitor) important an important precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector). d+1 c = 100 nf d-1 gnd dviulc6-4sc6 d+2 d-2 v cc 1 dvi connector side v cc (+5v) c=100 nf esd surge test board dviulc6-4sc6h
DVIULC6-4SC6Y technical information doc id 018878 rev 2 9/12 3.4 crosstalk behavior figure 17. crosstalk phenomena the crosstalk phenomena is due to the coupling between 2 lines. the coupling factor ( ? 12 or ? 21 ) increases when the gap acro ss lines decreases, particularly in silicon dice. in the example above the expected signal on load r l2 is ? 2 v g2 , in fact the real voltage at this point has got an extra value ? 21 v g1 . this part of the v g1 signal represents the effect of the crosstalk phenomenon of line 1 on line 2. this phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. the perturbed line will be more affected if it works with low voltage signal or high load impedance (few k ? ). figure 18. analog crosstalk measurements figure 18 gives the measurement circuit for the anal og application. in usual frequency range of analog signals (up to 240 mhz) the effect on disturbed line is less than -45 db (see figure 8 ). as the DVIULC6-4SC6Y is designed to protect high speed data lines, it must ensure a good transmission of operating signals. the frequency response ( figure 5 ) gives attenuation information and shows that the DVIULC6-4SC6Y is well suitable for data line transmission up to 1.65 gb/s. line 1 line 2 v g1 v g2 r g1 r g2 drivers r l1 r l2 receivers + 1 12 v g1 v g2 + 2 21 v g2 v g1 spectrum analyser 50 w tracking generator vg 50 w test board c=100nf spectrum analyser v out 50 tracking generator v g v in 50 test board v cc c=100nf dviulc6
package information DVIULC6-4SC6Y 10/12 doc id 018878 rev 2 4 package information epoxy meets ul94, v0 lead-free package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 19. footprint - dimensions in mm (inches) table 3. sot23-6l dimensions ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.90 1.45 0.035 0.057 a1 0 0.15 0 0.006 a2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.020 c 0.09 0.20 0.004 0.008 d 2.80 3.05 0.11 0.118 e 1.50 1.75 0.059 0.069 e0.95 0.037 h 2.60 3.00 0.102 0.118 l 0.30 0.60 0.012 0.024 ? 0 10 0 10 a2 a l h c b e d e e a1
DVIULC6-4SC6Y ordering information doc id 018878 rev 2 11/12 5 ordering information 6 revision history table 4. ordering information order code marking package weight base qty delivery mode DVIULC6-4SC6Y dl4y sot23-6l 16.7 mg 3000 tape and reel table 5. document revision history date revision changes 24-may-2011 1 first issue. 06-sep-2012 2 updated dimension a1 max., b min., and l min. in ta b l e 3 .
DVIULC6-4SC6Y 12/12 doc id 018878 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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